LDPC codes are a class of error correction codes invented in 1960 by Robert Gallager of MIT (“Massachusetts Institute of Technology”), constituting an alternative to the Viterbi codes as well as to the more recent turbo codes. LDPC codes are block codes which allow approaching the Shannon Limit. The first commercial standard stipulating the use of an LDPC code is the DVB-S2 standard, which is the second-generation ETSI (“European Telecommunication Standardization Institute”) standard for satellite digital video broadcasting. LDPC coding is included in it for channel coding, to protect the sent data from noise affecting the transmission channel.
With reference to FIG. 1, a generic transmission subsystem contains, on the side of the transmitter 10, a data source 11 (denoted DAT_SRC in the figure), followed by a source encoder 12 (denoted SCR_ENC in the figure), a channel encoder 13 (denoted CH_ENC in the figure), and a modulator 14 (denoted MOD in the figure). The source encoder 12 compresses the data (for example using a standard such as MPEG, H264, etc.) so as to reduce the bit rate of the data to be transmitted. The channel encoder adds redundancy (for example by using an LDPC code) to enable the receiver 30 to correct potential errors due to the noise No introduced into the transmission channel 20. The modulator 14 adapts the signal to the transmission channel (for example, satellite transmission channel, radio transmission channel, etc.). On the receiver side 30, a demodulator 34 (denoted DEMOD in the figure), followed by a channel decoder 33 (denoted CH_DEC in the figure), and a source decoder 32 (denoted SRC_DEC in the figure), perform operations dual to those performed by the modulator 14, the encoder 13, and the encoder 12, respectively. The demodulated and decoded data are then restored to the entity that uses the data 31 (denoted DAT_U in the figure).
LDPC codes are block codes. On the transmitter side, the LDPC encoder processes blocks of K information bits, and outputs code words of N bits, also called LDPC frames, where N>K. In other words, it adds N−K redundancy bits which enable the correction of transmission errors on the receiver side. These N−K bits are called parity bits. The code rate is defined as the ratio r=K/N. The smaller the r, the higher the redundancy, and therefore the higher the protection against noise in the transmission channel.
The N−K bits added to each block of K information bits are calculated using an H matrix, called the parity check matrix. This H matrix has N−K rows and N columns. It contains “0” and “1” values, with the latter in low proportions, which is why codes based on such a parity matrix are called low density parity check codes.
With reference to FIG. 2, an N-bit LDPC frame, in which the K low order bits correspond to the information bits and the N−K high order bits correspond to the parity bits, is the code word C delivered by an LDPC encoder which satisfies the relation:H×Ct=0  (1)
The check node degree for a row in the H matrix is the number of “1” values in the row, and the bit node degree for a column in the H matrix is the number of “1” values in the column. There exist two types of LDPC code: regular codes and irregular codes. The H matrix for a regular code has a constant number of “1” values per row and per column, meaning that the check node degrees and bit node degrees are constant. Conversely, the H matrix for an irregular code does not have constant check node degrees and/or bit node degrees, and is therefore more random in character. The best performance is obtained with irregular codes, but the decoding may then be more difficult. The DVB-S2 standard recommends the use of an H matrix which has constant check node degrees of between 4 and 30 (abbreviated as the matrix check node degree), and bit node degrees which may assume three values between 2 and 13.
On the receiver side, the LDPC decoder corrects the erroneous bits by using the relations between the bits in the LDPC frames received through the transmission channel, corresponding to a block of bits C′. These relations are given by the parity check matrix H, which is also known to the decoder.
To this effect, the errors in the received block of bits C′ are corrected by applying an iterative algorithm so that the corrected block of bits C′ satisfies the relation:C′×Ht=0  (2)
More particularly, the LDPC decoder processes likelihood ratios, for example log-likelihood ratios (LLRs). On the receiver side, there is an LLR for each of the N bits of an LDPC frame which was sent from the transmitter. For a transmitted bit d which has a corresponding signal x received by the LDPC decoder after noise is added to the transmission channel, the LLR ratio for the bit d in relation to the signal x is defined as:
      LLR    ⁡          (      x      )        =            LLR      ⁡              (                  d          /          x                )              =          ln      ⁢                        P          ⁡                      (                          d              =                              0                /                x                                      )                                    P          ⁡                      (                          d              =                              1                /                x                                      )                              where P(d=0/x) is the probability that the transmitted bit d is equal to 0 as a function of the value x received, and P(d=1/x) is the probability that the transmitted bit d is equal to 1 as a function of the value x received. Each LLR is coded in m bits. For example, an LLR assumes negative or positive values of greater absolute value as the probability that the received bit with which it is associated is equal, for example, to 0 or 1 respectively.
The LDPC decoder uses internal metrics, equal in number to the number of “1” values in the H matrix. These metrics are each coded in t bits. The decoder updates them using an iterative algorithm.
With reference to FIG. 3, each iteration comprises update steps performed by row, comprising determining for each row the first new values for the internal metrics of the row as a function of the other internal metrics of the row (“check node update”), then update steps performed by column, comprising determining for each column the second new values for the internal metrics of the column as a function of the other internal metrics of the column and the LLR corresponding to this column (“bit-node update”). To decode a received LDPC frame, the decoder performs several iterations in order to restore a block of N data sent. The decoded bits, called hard decision bits, are then obtained by adding the internal metrics by column with the LLRs for the C′ block received, and taking the sign of the result.
In traditional decoders, a given number of iterations of the iterative encoding algorithm are executed before the hard decision bits are obtained. This number is set in advance to a value considered to be sufficient to guarantee satisfactory decoding under any transmission conditions.
In FIG. 4, the top graph shows the curve 410 giving the Binary Error Rate (“BER”) observed on the receiver side as a function of the signal-to-noise ratio (“SNR”) in decibels (dB) defined on the transmitter side. The bottom graph shows the curve 420 graphing the power PWR in watts (W) used by the decoder on the receiver side as a function of the SNR of the transmission.
A peak 421 is observed in the power consumption of the decoder in the waterfall region 411 of the BER, followed by a plateau 422 in the decoder consumption. The operating range is located to the right of a vertical line 412 which marks the end of the waterfall region of the BER, where the BER is sufficiently low to guarantee the quality of the reception. For an SNR value corresponding to said vertical line 412, the value of the power consumed PWR is close to the value of the plateau 422.
Currently there is an attempt to reduce the amount of power used by the decoder, in order to push back the limits this imposes on greater silicon integration of systems incorporating it. In other words, the attempt is to reduce the value of the consumption plateau for a given SNR ratio.
One solution for limiting decoder consumption would include stopping the iterations of the iterative decoding algorithm as soon as the above relation (2) is satisfied. This would save the power corresponding to superfluous iterations in the decoding algorithm. The number of iterations would therefore be variable, corresponding to the minimum number of iterations required to obtain satisfactory decoding under actual transmission conditions.
Advantageously, the decoding would also be faster, which would be valuable in certain applications. However, implementation of this solution requires the use of hardware comprising RAM memory (Random Access Memory) having a storage capacity of several tens of kilobits (Kbits), a mixer for translating the structure of the H matrix, and ROM memory (Read Only Memory) for storing the location of the “1” values in the H matrix in order to allow controlling the mixer and managing the RAM read/write addresses. This hardware occupies a silicon surface area of approximately 0.4 to 0.5 mm2 in 90 nm CMOS technology. In addition, with this solution it is difficult to use the equivalent hardware resources already present in a traditional decoder, without complicating it to a dissuasive extent.